1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device having a super junction structure and a method of manufacturing the same.
2. Description of the Related Art
In recent years, there has been an increasing demand for reductions in thickness and weight of electronic apparatuses represented by liquid crystal televisions, plasma televisions, organic electroluminescence (EL) televisions, and the like. Attendant on the demand, the request for power supply apparatuses having a reduced size and an enhanced performance has also been becoming stronger. In response to the request, concern about power semiconductor devices has come to be focused on realization of improved performance, such as higher withstand voltage, larger current, lower loss, higher operating speed, and higher breakdown voltage. For example, as a switching element suitable for power electronics application, power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is known.
The ON-state resistance and withstand voltage of MOSFETs are heavily dependent on the impurity concentration in the N region serving as a conduction layer. The impurity concentration in the conduction layer may be increased in order to lower the ON-state resistance, but, for securing a desired withstand voltage, it is difficult to raise the impurity concentration beyond a certain value. In a MOSFET, the semiconductor region connecting the source region and the drain region to each other is generally called a drift region (drift layer). When the MOSFET is in the ON state, the drift region forms a current path, and when the MOSFET is in the OFF state, the withstand voltage of the MOSFET is maintained by a depletion layer extending from a p-n junction formed between the drift region and the base region.
The ON-state resistance of a MOSFET depends on the electric resistance of the conduction layer (drift region). For realizing a lower ON-state resistance, it may be contemplated to raise the impurity concentration in the drift region, thereby lowering the electric resistance of the drift region. When the impurity concentration in the drift region is increased, however, the extension of the depletion layer would become insufficient, and the withstand voltage would be lowered accordingly. In short, although a lower resistance can be realized by raising the impurity concentration in the drift region, there is a limit to the raising of the impurity concentration, because of the need to secure a desired withstand voltage. Thus, in MOSFETs, a lowered ON-state resistance and an enhanced withstand voltage are in a trade-off relation, and an improvement of this trade-off is being demanded in relation to lower-power-consumption devices.
As a technique for breaking through the trade-off, there is known a technology called a multi-RESURF (reduced surface field) structure or a super junction structure (hereinafter the term “super junction” will be used representatively). The following five documents are cited as relevant to the present invention: Japanese Patent Laid-open Nos. 2002-280555, 2006-005275, 2007-096344, 2007-173418, 2007-116190 (which are here referred to as Patent Documents 1 to 5, respectively).
As shown in Patent Documents 1 to 5, a MOSFET having a drift region of a super junction structure has a configuration in which pillar-shaped p-type semiconductor regions (P regions, p-type pillar regions, p-type vertical RESURF layer) and pillar-shaped n-type semiconductor regions (N regions, n-type pillar regions, n-type vertical RESURF layer) are arranged, alternately or in island form, periodically in a direction parallel to the surface of a semiconductor substrate. Specifically, the MOSFET has a vertical RESURF structure in which p-type pillar regions and the n-type pillar regions are alternately provided repeatedly in a lateral direction, in the semiconductor layers disposed on both sides of the source and drain electrodes.
The withstand voltage is maintained by the depletion layers extending from p-n junctions formed by these semiconductor regions. Even when the extension of the depletion layers is reduced due to an increase in the impurity concentration for obtaining a lowered ON-state resistance, thorough depletion of the semiconductor regions can be achieved by narrowing the width of the semiconductor regions. In the ON state, the N regions of the conduction layer permit a current to flow, whereas in the OFF state, the P regions and the N regions are thoroughly depleted, whereby the withstand voltage can be secured. Consequently, a MOSFET having both a lowered ON-state resistance and an enhanced withstand voltage at the same time can be realized.
Thus, in the super junction structure, the ON-state resistance and the withstand voltage depend on the width of each of the p-type semiconductor regions and the width of each of the n-type semiconductor regions which are each sandwiched between the p-type semiconductor regions. When the respective widths of the p-type semiconductor regions and the n-type semiconductor regions are narrowed further, the impurity concentration in the n-type semiconductor regions can be further raised, whereby a further lowered ON-state resistance and a further enhanced withstand voltage can be attained. From this, it is obvious that the impurity concentration is the point in determining the withstand voltage and the ON-state resistance.
Therefore, in a preferred embodiment, it may be important for a further enhancement of the withstand voltage to make favorable the balance between the impurity in the p-type semiconductor regions and the impurity in the n-type semiconductor regions, i.e., the so-called charge balance. To be more specific, the amount of the impurity contained in the p-type semiconductor region and that in the n-type semiconductor region may be equalized, whereby the impurity concentration is made to be zero on an equivalent basis, and an enhanced withstand voltage can be obtained. In this manner, while a high withstand voltage is maintained by contriving thorough depletion of the P and N regions at the time of a reverse bias (OFF time), a current is permitted to flow through the n-type semiconductor regions doped with the impurity at a high concentration at the time of zero bias (ON time), whereby a device with a lowered ON-state resistance which has been improved beyond the material-based limits can be realized.
In addition, in a semiconductor device having a super junction structure, the withstand voltage and the avalanche withstand capability depend not only on the structure of the region of active operation of the semiconductor device (this region is called a device portion, a device active region portion, an active region portion, a cell region portion, a device body portion or the like, and will hereinafter be referred to representatively as “device portion”) but also on the structure of the region so provided as to surround the device portion (this surrounding portion is called a terminal portion, a device periphery portion, a peripheral structure portion, a junction terminal region portion or the like, and will hereinafter be referred to representatively as “terminal portion”).
When a difference in the manner of spreading of the depletion layer exists between the device portion and the terminal portion, a difference in optimal impurity concentration would also exists between the two portions. If the device portion and the terminal portion are so produced to have the same impurity amount, therefore, the withstand voltage may be lowered in the terminal portion, and an electric field may be concentrated on the part where the withstand voltage is thus lowered, resulting in breakage of the device. Thus, the device as a whole may fail to have a sufficient withstand voltage.
Besides, where the terminal portion is not provided with the super junction structure, the occurrence of avalanche breakdown would cause, due to electrons and holes generated, an increase in the electric field in an upper part and a lower part of the terminal portion, whereby the breakdown current would be increased, possibly leading to the breakage of the device. In other words, the avalanche breakdown voltage is low in this case.
Taking these points into consideration, it also seems necessary in the case of a MOSFET having a super junction structure to appropriately design the structure of the device portion and the structure of the terminal portion, respectively. Techniques for solving this problem are generally classified into two approaches: one in which a measure is taken while providing also the terminal portion with a super junction structure, and the other in which a measure is taken while not providing the terminal portion with a super junction structure. Patent Documents 2 to 5 each make a proposal relating to a terminal portion structure in which the former approach is adopted.
In a mechanism (or setup) described in Patent Document 2, a device portion is provided with a super junction structure, specifically, a structure including first pillar regions of a first conductivity type and second pillar regions of a second conductivity type. On the other hand, a terminal portion is provided with a super junction structure which is adjacent to the super junction structure of the device portion and of which the thickness in the vertical direction is smaller than that in the device portion. Further, for securing a withstand voltage in the terminal portion, the impurity concentration in n-type semiconductor regions in the terminal portion is set lower than the impurity concentration in n-type semiconductor regions in the device portion. For example, in the terminal portion, third pillar regions of the first conductivity type and fourth pillar regions of the second conductivity type are formed. Besides, in the state of being layered over the third or fourth pillar region, closest to the device portion, of the super junction structure of the terminal portion, an outermost pillar region lower than the first and second pillar regions in impurity concentration is additionally formed at the outermost portion, closest to the terminal portion, of the super junction structure of the device portion. Further, a high-resistance layer of the first conductivity type higher in resistance than the pillar regions is formed over the third pillar regions and the fourth pillar regions.
In Patent Document 3, also, for securing a withstand voltage in a terminal portion, the impurity concentration in n-type semiconductor regions in the terminal portion is set lower than the impurity concentration in n-type semiconductor regions in a device portion. For instance, the ion implantation area for a second conductivity type partition region on the outermost side is set to be smaller than the ion implantation area for each region of parallel p-n layer on the inner side thereof, so as to ensure that the second conductivity type partition region on the outermost side and each region of parallel p-n layer on the inner side thereof are approximately equal in net amount of impurity.
In Patent Document 4, similarly, a terminal portion is provided with a super junction different from that provided in a device portion. For example, n-type regions and p-type regions are provided in parallel over a principal surface of an n+ layer in the terminal portion, a high-resistance semiconductor layer is provided over the n-type regions and the p-type regions, and n-type regions and p-type regions are provided in parallel over the high-resistance semiconductor layer. The impurity concentration in at least one kind of n-type pillar regions and p-type pillar regions is gradually varied along the direction of from a first main electrode (source electrode) toward a second main electrode (drain electrode) so that the amount of impurity in the n-type pillar region is smaller than the amount of impurity in the p-type pillar region on the first main electrode side, whereas the amount of impurity in the n-type pillar region is larger than the amount of impurity in the p-type pillar region on the second main electrode side.
In Patent Document 5, in the case of forming a device portion in which a drift current flows and a terminal portion surrounding the device portion, the terminal portion is provided with a second n-type drift layer and a second p-type drift layer formed along at least one of two directions which are orthogonal to each other.
On the other hand, as a method for fabricating a super junction structure, the following three techniques may be considered.
(1) A method in which an n-type impurity and a p-type impurity are each individually introduced into an epitaxial layer (epitaxial silicon) by ion implantation, and the epitaxial structure is layered repeatedly a number of times (this method will be referred to as first fabrication method). This is a multi-epitaxial fabrication method in which similar epitaxial growth is repeated a number of times.(2) A method in which trenches are formed in a thick epitaxial layer, an impurity is provided at side surfaces of each of the trenches by such method as diffusion, and an insulating material or a non-conducting material is buried there (this method will be referred to as second fabrication method).(3) A method in which trenches are formed in a thick epitaxial layer, and the trenches are filled up with impurity-containing silicon by epitaxial growth (this method will be referred to as third fabrication method). This is a method in which the trenches once formed are backfilled by epitaxial growth (a trench forming and epitaxially backfilling fabrication method).